1. Field of the Invention.
The present invention relates generally to and transistors and circuits made using transistors. In particular, the present invention relates to input/output (I/O) buffers made using metal-oxide-semiconductor field-effect transistors (MOSFETs). Still more particularly, the present invention relates to an input/output buffer that can be coupled to circuits having a higher operating voltage level without affecting the performance of the input/output buffer.
2. Description of the Background Art.
In the area of semiconductors, there is a continuing need for integrated circuits that have more transistors, thereby allowing more complicated and elaborate circuitry to be created on a single chip and enabling the chip to provide even greater functionality and computational power than is presently available. There is also a need to have integrated circuits consume less power since the number of transistors included within an integrated circuit is ever increasing. Furthermore, there is a need for increased switching speeds for the transistors since the operational clock speeds of integrated circuits are also ever increasing. These competing needs have caused the generation of mixed voltage integrated circuits where different portions of the circuits have different operating voltages and are created with different processes. For example, present day integrated circuits include mixed voltage scenarios having higher voltage portions operating at five (5) volts and created with a five volt (5 V) process, and lower voltage portions operating at three (3) volts and created with a three volt (3 V) process.
One problem with such mixed voltage integrated circuits is connecting portions of the circuit having different operating voltages. The differential in operating voltages causes device failure and inaccurate operation in the transistors connecting ("connecting transistors") the lower voltage portions to the higher voltage portions because of the increased stress placed on the connecting transistors designed for operation at the lower voltage. Typically, the semiconductor fabrication process used to create the lower voltage portions, for example a 3 V process creates devices using thinner layers of semiconductor materials than those used the fabrication process to create the higher voltage portions of the integrated circuit. The process migration has been driven by the desire for improved performance with circuits that consume less power, have greater switching speeds and require less materials to manufacture because the wells of the transistors are more shallow and the gate oxide thicknesses are reduced. The difference in thickness used in these processes affects the leakage current of transistors and in turn the overall reliability of mixed voltage circuits. A 5 V voltage difference between gate-drain, gate-source or source-drain can cause sufficient degradation in the performance of the transistors, especially in 3 V process transistors.
One prior art approach used to reduce the instances of device failure for connecting transistors has been to increase the thickness of some of the low operating voltage portions of the integrated circuit, specifically the connecting transistors. For example, the prior art has used a "dual oxide" for core areas where the lower operating voltage portions of the integrated circuit interface with the higher perating voltage portions of the integrated circuit. Use of "dual oxide" especially for the gate oxide reduces the reliability problems of the connecting transistors, however, the use of dual oxide creates other problems. In particular, the use of dual oxide makes the manufacturing process more difficult by adding undesirable levels of complexity and cost. Furthermore, the use of dual oxide changes the threshold voltages of the transistors and also degrades the switching speed of the connecting transistors, and creates a bottleneck limiting the rate at which data can be transmitted from in and out of the integrated circuit.
Yet another prior art approach used reduce the instances of device failure for connecting transistors is the use of a floating well as part of the connecting transitors. A transistor with a floating well is a MOSFET transistor having a well that switches between being coupled to a higher operating voltage (i.e., 5 volts) and a lower operating voltage (i.e., 3 volts). The switching between voltages is triggered by the charge and discharge of the well once the higher operating voltage is applied to and removed from the transistor. However, the problem with the use of floating wells is that it is difficult to predict the charging and discharging times for particular wells. Furthermore, the charging and discharging times are highly dependent on the layout pattern and operation of the circuit.
Therefore, there is a continuing need for an input/output buffer that can be used a mixed voltage circuit without the device failure of the prior art. Such an input/output buffer must be easy to manufacture and not suffer from switching speed delays.